Dual Stack Conditional Push-Pull Pulsed Latches

In this paper, a novel class of pulsed latches of high speed under minimum energy consumption is designed and implemented in 65-nm CMOS technology. This conditional push-pull pulsed latch adopts a push-pull output stage, which is driven by two split paths with a conditional pulse generator. It is implemented in two versions, respectively, without (CP 3 L) and with (CSP 3 L) shareable conditional pulse generator. The implemented pulsed latch outperforms the well known transmission gate pulsed latch (TGPL). The CP 3 L and CSP 3 L designs are faster than transmission gate pulsed latch (TGPL) by 2.01X (1.19X) for the minimum ED design. The incremented energy dissipation is further reduced by employing dual stack approach. Keywords— Flip-flops(FFs), leakage power, low power techniques, nanometer CMOS, process technologies, pulsed latches, VLSI.